There are several types of semiconductor integrated circuit devices where external connections, e.g., bond pads, are placed on the “back side” of the device, i.e., on the side of the semiconductor substrate opposite to the side with most of the metallization layers.
FIG. 1a provides a side cross-sectional view of two chip scale package (CSP) devices 10, 12 that include CMOS image sensors. FIG. 1a shows the two devices 10, 12 connected to a carrier substrate 14, such as a carrier wafer, via an appropriate connection. The devices 10, 12 further include bond pads 20, 22 and corresponding solder bumps 24, 26, respectively, on the back side of the devices. Metal interconnects 30, 32 connect the bond pads 20, 22 to the front side of the device 10, 12, respectively.
FIG. 1b provides a top view of the two CSP devices 10, 12 and a scribe area 40 there between. Each device 10, 12 actually includes several bond pads, including a row of pads 42, 44 and extension pads 46, 48, respectively. The scribe area 40 includes a scribe line 50 and a pair of seal rings 52, 54.
Several problems exist with the above-described devices. For one, the number of pads must be doubled due to the extension pads, which requires extra space and enlarge chip size. Another problem is that an outer dielectric film is subject to cracking and moisture. The metal interconnects also present reliability problems.
FIGS. 1c and 1d further provide sectional views of the CSP device 10 with more details. Formed on the substrate 62 are interconnection 64 and the passivation layer 66. A metal pad 68 is formed on the interconnection 64. Then a dielectric film 70, such as a dry film, is formed on the passivation layer and is further patterned. A metal structure 72 is formed within the opening of the patterned dielectric film. The metal structure 72 includes a metal post 74 contacting the metal pad 68 and a through silicon via (TSV) metal post 76. Then the patterned dielectric film 70 is removed, leaving the metal structure 72 extruded from the passivation layer 66, as illustrated in FIG. 1d. The top surface of the metal structure 72 and the top surface of the passivation layer 66 have a step height, causing packaging issues and associated device performance concerns.